Analysis of Vedic Multiplier for Conventional CMOS and Complementary Pass Transistor Logic (CPL) Logics

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S. Nagaraj
K. Venkatramana Reddy
P. Anil Kumar

Abstract

In this work we have designed and analyzed Vedic Multiplier for conventional CMOS and Complementary Pass Transistor Logic (CPL). Vedic Multiplier is designed for 4-bit and 8-bit using conventional CMOS gates and CPL gates. Their Speed, Area and Power is analyzed and compared. The design is implemented using HSPICE for 180nm Technology.

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How to Cite
1.
Nagaraj S, Reddy K, Kumar P. Analysis of Vedic Multiplier for Conventional CMOS and Complementary Pass Transistor Logic (CPL) Logics. sms [Internet]. 30Nov.2020 [cited 18Apr.2021];12(SUP 3):94-8. Available from: https://smsjournals.com/index.php/SAMRIDDHI/article/view/2208
Section
Review Article