Implementation of Low Power DFT for ASIC SOC
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Abstract
In System on Chip (SoC), a low power DFT technique plays a crucial role to reduce power consumption. These low power
techniques throw a major challenge for the designers and verification engineers. Different low power DFT techniques
like multiple Supply Voltages, Power Switches, clock gating, low power isolation cells and so on are applied at various
stages of DFT flow. In this brief, the primary focus is to reduce the dynamic power consumption of a digital circuit in
the scan Synthesis phase. Here a common clock is connected to all scan flip-flops with a frequency of 40MHz.Without
any timing violations, the clock frequency is reduced to 20MHz thereby ensuring that there is a reduction in dynamic
power consumption to a value of 50%.
techniques throw a major challenge for the designers and verification engineers. Different low power DFT techniques
like multiple Supply Voltages, Power Switches, clock gating, low power isolation cells and so on are applied at various
stages of DFT flow. In this brief, the primary focus is to reduce the dynamic power consumption of a digital circuit in
the scan Synthesis phase. Here a common clock is connected to all scan flip-flops with a frequency of 40MHz.Without
any timing violations, the clock frequency is reduced to 20MHz thereby ensuring that there is a reduction in dynamic
power consumption to a value of 50%.
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How to Cite
1.
Durgagopal R, Rao D. Implementation of Low Power DFT for ASIC SOC. sms [Internet]. 25Dec.2019 [cited 17Jun.2025];12(SUP 3):1-. Available from: https://smsjournals.com/index.php/SAMRIDDHI/article/view/2207
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Research Article
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