Ultra-Low Power Stacked nMOS m-Sequence Code Generator with Reduced Leakage Power for Body Sensor Node Applications
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Abstract
The rapid increase in population which is itself leading to a varied type of diseases is throwing a challenge to the
medical technology nowadays. Body Sensor nodes (BSNs) are the devices which are used for the real time monitoring of
the patient’s condition. These BSNs were very helpful in exact analysis of the condition of the patients without any kind
of the physical operation. The BSNs thus has to work efficiently for the outmost applications. The power consumption of
such devices comprises of many factors which includes leakage power. The leakage power can be reduced using the
stacking technique. In this paper, nMos stacking technique is used to reduce the leakage power of m-sequence code
generator which is the main block in transmitter of BSN. Such reduction of the leakage power will lead to increase in the
energy efficiency of the BSN. 90nm CMOS technology is used to simulate the proposed m-sequence code generator. The
simulation results have shown that the proposed m-sequence code generator has less average power by having less
leakage power.
medical technology nowadays. Body Sensor nodes (BSNs) are the devices which are used for the real time monitoring of
the patient’s condition. These BSNs were very helpful in exact analysis of the condition of the patients without any kind
of the physical operation. The BSNs thus has to work efficiently for the outmost applications. The power consumption of
such devices comprises of many factors which includes leakage power. The leakage power can be reduced using the
stacking technique. In this paper, nMos stacking technique is used to reduce the leakage power of m-sequence code
generator which is the main block in transmitter of BSN. Such reduction of the leakage power will lead to increase in the
energy efficiency of the BSN. 90nm CMOS technology is used to simulate the proposed m-sequence code generator. The
simulation results have shown that the proposed m-sequence code generator has less average power by having less
leakage power.
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How to Cite
Sekhar Reddy, S., Revanth, T., & Musala, S. (2019). Ultra-Low Power Stacked nMOS m-Sequence Code Generator
with Reduced Leakage Power for Body Sensor Node
Applications. SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology, 12(SUP 3), 89-93. https://doi.org/10.18090/samriddhi.v12iS3.20
Section
Research Article
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
References
[1] Abdulfattah AN, Tsimenidis CC, Yakovlev A. “Ultra-low power m-sequence code generator for body sensor node applications”.
Integration, the VLSI Journal 2017
[2] S.V.Raghu Sekhar Reddy, T.N.S.R.Revanth, Sarada Musala, “Ultra low power m-sequence code generator using new XOR gate for body sensor node applications”, International Conference On Commnication and Signal Processing, IEEE, 2019, pp. 0577–0581.
[3] Sreenivasa Rao Ijjada, B. Ramparamesh, “Reduction of Power Dissipation in Logic Circuits”, International Journal of Computer Applications, Vol. 29-No. 6, June 2011.
[4] Q. Zhang, P. Feng, Z. Geing, X. Yan, N. Wu, A 2.4- GHz energy-efficient transmitter for wireless medical applications, IEEE Trans. Biomed. Circuits Syst. 5, 2011 pp.39–47.
[5] N. Reynders and W. Dehaene, “Variation- resilient sub-threshold circuit solutions for ultra-low-power Digital Signal Processors with 10MHz clock frequency,” in Proc. ESSCIRC, Sep. 2012, pp. 474–477.
[6] D.vijayalakshmi, Dr P.C Kishore Raja, “Leakage Power Reduction Techniques in CMOS VLSI Circuits – A Survey”, May 2016 IJSDR | Volume 1, Issue 5.
[7] Karunakar Reddy Kallam, Pradeep Karumanchi, “Leakage Power in CMOS and Its Reduction Techniques”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 4, Issue 9, September 2015.
[8] Satish Kumar Nalluri, Venkata Krishna Bharadwaj Parasaram. (2019). Software-Centric Automation Frameworks Integrating AI and Cybersecurity Principles. International Journal of Engineering Science & Humanities, 9(1), 30–40. Retrieved from https://www.ijesh.com/j/article/view/539
[9] P. K. Sharma, B. Bhargava, S. Akashe, “Reduction of Leakage Power in Digital Logic Circuits Using Stacking Technique in 45 Nanometer Regime”, World Academy of Science, Engineering and Technology International Journal of Electronics and Communication Engineering Vol:7, No:1, 2013.
[10] Ankita Nagar, Vidhu Parmar, “Implementation of Transistor Stacking Technique in Combinational Circuits” , IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 5, Ver. I (Sep-Oct. 2014), PP 01-05
Integration, the VLSI Journal 2017
[2] S.V.Raghu Sekhar Reddy, T.N.S.R.Revanth, Sarada Musala, “Ultra low power m-sequence code generator using new XOR gate for body sensor node applications”, International Conference On Commnication and Signal Processing, IEEE, 2019, pp. 0577–0581.
[3] Sreenivasa Rao Ijjada, B. Ramparamesh, “Reduction of Power Dissipation in Logic Circuits”, International Journal of Computer Applications, Vol. 29-No. 6, June 2011.
[4] Q. Zhang, P. Feng, Z. Geing, X. Yan, N. Wu, A 2.4- GHz energy-efficient transmitter for wireless medical applications, IEEE Trans. Biomed. Circuits Syst. 5, 2011 pp.39–47.
[5] N. Reynders and W. Dehaene, “Variation- resilient sub-threshold circuit solutions for ultra-low-power Digital Signal Processors with 10MHz clock frequency,” in Proc. ESSCIRC, Sep. 2012, pp. 474–477.
[6] D.vijayalakshmi, Dr P.C Kishore Raja, “Leakage Power Reduction Techniques in CMOS VLSI Circuits – A Survey”, May 2016 IJSDR | Volume 1, Issue 5.
[7] Karunakar Reddy Kallam, Pradeep Karumanchi, “Leakage Power in CMOS and Its Reduction Techniques”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 4, Issue 9, September 2015.
[8] Satish Kumar Nalluri, Venkata Krishna Bharadwaj Parasaram. (2019). Software-Centric Automation Frameworks Integrating AI and Cybersecurity Principles. International Journal of Engineering Science & Humanities, 9(1), 30–40. Retrieved from https://www.ijesh.com/j/article/view/539
[9] P. K. Sharma, B. Bhargava, S. Akashe, “Reduction of Leakage Power in Digital Logic Circuits Using Stacking Technique in 45 Nanometer Regime”, World Academy of Science, Engineering and Technology International Journal of Electronics and Communication Engineering Vol:7, No:1, 2013.
[10] Ankita Nagar, Vidhu Parmar, “Implementation of Transistor Stacking Technique in Combinational Circuits” , IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 5, Ver. I (Sep-Oct. 2014), PP 01-05