Low Power CMOS Dynamic Latch Comparator using 0.18μm Technology

Abstract

The design and analysis of low power, high speed CMOS dynamic latch comparator is presented. The comparator combines the features of both, the resistive dividing network and differential current sensing comparator. The proposed design will improve the comparator performance by reducing the propagation delay, power dissipation. Simulation results are obtained in 0.18um with supply voltages of 1.8v respectively. The schematic of comparator is captured using Cadence Virtuoso schematic editor and simulated using the Cadence Spectre simulator.