Optimizing and Recuperating the Leakages in Low Voltage CMOS Circuits

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Ambresh Patel
Ritesh Sadiwala

Abstract

With the advancement of technology, small and handy electronic devices are built with low supply voltage and lower power dissipation in designing deep submicron static CMOS circuits. Small devices scaling down with burst-mode type integrated circuits have two major challenges: area and power dissipation. This paper presents a method for decreasing dynamic power, area, and leakage of application-specific integrated circuits without sacrificing performance. The High Threshold Leakage Control Transistor, TG-Based Technique, Supply Voltage Scaling, Sleep Transistor approaches are covered, and a dynamic CMOS architecture with stack transistor. With certain area and delay considerations, these strategies are utilized to diminish both types of power dissipation in the CMOS logic designs.

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How to Cite
1.
Patel A, Sadiwala R. Optimizing and Recuperating the Leakages in Low Voltage CMOS Circuits. sms [Internet]. 30Jun.2022 [cited 8Aug.2022];14(02):202-5. Available from: http://smsjournals.com/index.php/SAMRIDDHI/article/view/2728
Section
Research Articles